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Journal Articles
2025
6. N Manzoor, W Manzoor, D Nandi, A K Dutta, and Y S Chauhan, “Characterization and Modeling of Fully-Depleted SOI Varactor with Independently-Controlled Front- and Back-Gates for RF Applications”, in IEEE Transactions on Electron Devices, 2025, doi: 10.1109/TED.2025.3566930.
5. Y H Zarkob, D Rajasekharan, A Pampori, A Sharma, G Pahwa, D Nandi, C K Dabhi, V Kubrak, B Peddenpohl, M Tang, C Hu, and Y S Chauhan, "Impact Ionization in LDMOS Transistors: Improved Compact Model and Asymmetry under Forward and Reverse Modes of Operation", IEEE Journal of the Electron Devices Society, 2025, doi: 10.1109/JEDS.2025.3529730.
4. D Nandi, C K Dabhi, D Rajasekharan, N Karumuri, S Turuvekere, B Swaminathan, S Srihari, A Dutta, C Hu, and Y S Chauhan, "Utilizing Symmetric BSIM-SOI SPICE model for Dynamically Depleted RF SOI T/R Switches and Logic Circuits," IEEE Journal of the Electron Devices Society, 2025, doi: 10.1109/JEDS.2024.3484295.
2024
3. D Nandi, C K Dabhi, D Rajasekaran, N Karumuri, S Turuvekere, S Choppalli, A S Pratiyush, C Hu, and Y S Chauhan, “Physical Insights and Accurate Modeling of Transconductance in Body-contacted Dynamically Depleted SOI MOSFETs”, IEEE Transactions on Electron Devices, 2024, doi: 10.1109/TED.2024.3461670.
2. C K Dabhi, D Rajasekaran, G Pahwa, D Nandi, N Karumuri, S Turuvekere, A Dutta, B Swaminathan, S Srihari, Y S Chauhan, C Hu, “Symmetric BSIM-SOI Part-I: A Compact Model for Dynamically Depleted SOI MOSFETs”, IEEE Transactions on Electron Devices, 2024, doi: 10.1109/TED.2024.3363110.
1. C K Dabhi*, D Nandi*, K Nandan, D Rajasekaran, G Pahwa, N Karumuri, S Turuvekere, A Dutta, B Swaminathan, S Srihari, Y S Chauhan, S Salahuddin, C Hu, “Symmetric BSIM-SOI Part-II: A Compact Model for Partially Depleted SOI MOSFETs”, IEEE Transactions on Electron Devices, 2024, doi: 10.1109/TED.2024.3363117. [*equal contribution]
Conference Papers:
​2025:
7. D Nandi, C K Dabhi, D Rajasekharan, N Karumuri, S Turuvekere, S Choppalli, A Dutta, C Hu, and Y S Chauhan, "Accurate Modeling of Sub-threshold region considering the impact of STI edge conduction in Surface potential-based BSIM-SOI Compact Model Framework" Accepted in the 2025 IEEE International Compact Modeling Conference, San Francisco, USA, 2025.
6. D Nandi, C K Dabhi, D Rajasekharan, N Karumuri, S Turuvekere, S S Parihar, A Pampori, A Dutta, C Hu, and Y S Chauhan, "Recent Enhancements in the Industry-Standard Surface potential-based BSIM-SOI Compact Model" Accepted in the 2025 IEEE International Compact Modeling Conference, San Francisco, USA, 2025.
5. N Manzoor, W Manzoor, D Nandi, A K Dutta, and Y S Chauhan, "Compact Modeling of Kink Effect in BULK MOSFETs at Cryogenic Temperatures," Accepted in the 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Hong Kong, China, 2025.
4. W Manzoor, N Manzoor, Y H Zarkob, D Nandi, A K Dutta, and Y S Chauhan, "Benchmarking of the BSIM-BULK for Cryo-CMOS Design", Accepted in the 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Hong Kong, China, 2025.
2024:
3. D Nandi, C K Dabhi, D Rajasekharan, N Karumuri, S Turuvekere, B Swaminathan, S Srihari, A Dutta, C Hu and Y S Chauhan, "Validation of Dynamically Depleted Symmetric BSIM-SOI Compact model for RF SOI T/R Switch Applications," 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, doi: 10.1109/EDTM58488.2024.10512295.
2. Y H Zarkob, A Sharma, G Pahwa, D Nandi, C Dabhi, V Kubrak, B Peddenpohl, M Tang, C Hu and Y S Chauhan, "Compact Modeling and Experimental validation of Reverse Impact Ionization in LDMOS transistors within the BSIM-BULK framework", 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, doi: 10.1109/EDTM58488.2024.10512085.
2017:
1. G Kumar, M Singh, G Trivedi, D Nandi "Bandgap generation in 2D materials", IEEE Conference on Devices for Integrated Circuit (DevIC), 2017, doi: 10.1109/DEVIC.2017.8074011
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